Formal Equivalence Checking and layout Debugging covers significant subject matters in layout verification: common sense equivalence checking and layout debugging. the 1st a part of the booklet reports the layout difficulties that require good judgment equivalence checking and describes the underlying applied sciences which are used to unravel them. a few novel ways to the issues of verifying layout revisions after in depth sequential variations equivalent to retiming are defined in element.
the second one a part of the ebook provides an intensive survey of earlier and contemporary literature on layout errors analysis and layout errors correction. This half additionally presents an in-depth research of the algorithms utilized in good judgment debugging software program courses, ErrorTracer and AutoFix, constructed through the authors.
From the Foreword:
`With the adoption of the static sign-off method of verifying circuit implementations the application-specific built-in circuit (ASIC) will adventure the 1st radical methodological revolution because the adoption of good judgment synthesis. Equivalence checking is among the serious components of this methodological revolution. This ebook is well timed for both the fashion designer trying to higher comprehend the mechanics of equivalence checking or for the CAD researcher who needs to enquire well-motivated learn difficulties equivalent to equivalence checking of retimed designs or mistakes prognosis in sequential circuits.'
Kurt Keutzer, college of California, Berkeley
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